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NXP Semiconductors /LPC43xx /CGU /BASE_SAFE_CLK

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Interpret as BASE_SAFE_CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLED)PD 0RESERVED0 (DISABLED)AUTOBLOCK 0RESERVED0CLK_SEL0RESERVED

PD=ENABLED, AUTOBLOCK=DISABLED

Description

Output stage 0 control register for base clock BASE_SAFE_CLK

Fields

PD

Output stage power down

0 (ENABLED): Enabled. Output stage enabled (default)

1 (POWER_DOWN): Power-down
RESERVED

Reserved
AUTOBLOCK

Block clock automatically during frequency change

0 (DISABLED): Disabled. Autoblocking disabled

1 (ENABLED): Enabled. Autoblocking enabled
RESERVED

Reserved
CLK_SEL

Clock source selection. All other values are reserved.

1 (IRC_DEFAULT): IRC (default)
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data